| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 101 | Design and Implementation of Multiplierless FIR Filter Authors:G. RAMBABU, K. GOVINDA RAO |
511-515 |
Download | |
| IJVDCS 102 | Implementation of An Efficient Low Power BIST Test Pattern Generator Using LP-LFSR Authors:V. KISHORE, T. KIRAN KUMAR |
516-522 |
Download | |
| IJVDCS 103 | Design of High Speed VLSI Architecture for MAC Based 1D/2D -DWT Authors:DASARI CHANTI, G. N. ANITHA PRIYADHARSHINI |
523-526 |
Download | |
| IJVDCS 104 | Performance Evaluation of Delay Optimized Parallel Adders Authors:CHUNDURI BHARGAVI, B. SURESH KUMAR |
527-529 |
Download | |
| IJVDCS 105 | Realization of Power Optimized MDC FFT Architecture Authors:TELAGATHOTI RAVI KUMAR, V. MAHESH |
530-533 |
Download | |
| IJVDCS 106 | Implementation of High-Performance Fast Pipelined DCT Architecture for HEVC Authors:JAVVADI SAMBASIVARAO, K. REDDEIAH |
534-537 |
Download | |
| IJVDCS 107 | A Novel Approach to Implement QCA Based Adders for High Speed Applications Authors:PRAMEELA DUMPALA, PAILA DALINAIDU |
538-542 |
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| IJVDCS 108 | A Novel Approach To Design Chien Search Architecture for Area Critical Applications Authors:MADASU PRAVEEN BABU, V. MAHESH |
543-546 |
Download | |
| IJVDCS 109 | A Novel 4096-Point Radix-4 Memory-Based FFT Using DSP Slices Authors:SHAIK KASHIK ALI, JABEENA SHAIK |
547-553 |
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| IJVDCS 110 | Recursive Approach to the Design of Parallel Self-Timed Adder Authors:YELLARI GEETHA, P. S. RAJA KUMAR, K. PRADEEP KUMAR |
554-558 |
Download | |
